This invention relates generally to a semiconductor integrated circuit device. More particularly, the present invention relates to a technique which will be effective when applied to a semiconductor integrated circuit device for constituting various gates by wiring basic cell transistors with one another.
A gate array is one of the semiconductor integrated circuit devices employing a master slice system which makes it possible to design a small quantity of various kinds of devices within a short period. The gate array is primarily used as an interface of a CPU (Central Processing Unit). The gate array inputs an external signal to a gate formed in a logic area through an input buffer circuit of a peripheral portion and outputs the output signal from the gate of the logic area to the outside through an output buffer circuit of the peripheral portion. Thus a large number of input buffer circuits and output buffer circuits are disposed at the peripheral portions of the semiconductor chip constituting the gate array. A power source voltage V.sub.cc, e.g. 5 V, must be supplied to transistors constituting these input and output buffer circuits while a reference potential V.sub.ss, e.g. a ground potential of 0 V, must be supplied also to them. The power source voltage V.sub.cc and reference potential V.sub.ss are supplied through power source wirings and reference voltage wirings that extend on the input buffer circuits and the output buffer circuits described above.